Vietsemi Technology maintains a broad portfolio of SoC building blocks that provide silicon proven IP for customers who need:
IPs | Description |
|---|---|
| AXI to APB | Bridge AXI to APB |
| AXI to AHB | Bridge AXI to AHB |
| AHB to AXI | Bridge AHB to AXI |
| SPI to I2C | Convert SPI to I2C interface |
| SPI to UART | Convert SPI to UART interface |
| Wishbone to APB | Bridge Wishbone to APB |
| PDM to PCM | PDM to PCM audio signal converter |
| PCM to PDM | PCM to PDM audio signal converter |
AXI2APB is a bridge to convert AXI bus into APB bus. The bridge is fully programmable, configurable, and flexible to customer's needs.
Asynchronous Reset
Compliant with AXI4 (IHI0022J_amba_axi) bus protocol
Compliant with APB bus protocol
Supports asynchronous clock domain
Supports narrow transfers
AXI4 and APB data widths are the same and support upto 256 bits
Programmable Registers
AXI2AHB is bridge to convert AXI bus into AHB bus. The bridge is fully programmable, configurable, and flexible to customer's needs.
Asynchronous Reset
Compliant with AXI4 (IHI0022J_amba_axi) bus protocol
Compliant with AHB 5C bus protocol
Supports asynchronous clock domain
Supports narrow transfers
AXI4 and AHB data widths are the same and support upto 256 bits
Programmable Registers
AHB2AXI is bridge to convert AHB bus into AXI bus. The bridge is fully programmable, configurable, and flexible to customer's needs.
Supports asynchronous clock domain
AHB and AXI data widths are the same and support upto 256 bit
Supports narrow transfers
Programmable Registers
Supports burst termination on the AHB
Timeout feature to indicate no response from AXI
SPI2I2C is a bridge that converts data between SPI and I2C standards.
SPI clocking modes 0, 1, 2, and 3 are supported
Programmable Clock polarity and phase (CPOL and CPHA)
Transfer data bit MSB first
I2C-bus slave interface operating up to 400 kHz
Uses 7-bit slave addressing
Use separated Async. FIFO for Transmitting and Receiving Data, with programmable user-specified on runtime-changeable levels
SPI2UART is a bridge that converts data between SPI and UART standards.
Compliant with SPI and UART Protocol
Programmable data length UART (8 bits)
Programmable 1, 2 bit Stop
Programmable Data Direction (LSB first or MSB first)
Programmable Clock polarity and phase (CPOL and CPHA) - 4 mode
Programmable parity mode
Configurable oversampling support (8x, 16x)
Vietsemi Technology provides ...
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PDM2PCM IP receives the 1-bit PDM signal from microphone and converts to 16-bit PCM with high Signal-to-Noise Ratio (SNR) and small distortion. DTI_PDM2PCM IP optimizes hardware usage to archive better power consumption and area.
Single channel 1-bit PDM audio input from MEMS microphone with 1 to 3,072 kHz sampling rate, typically use 2,304 kHz
Single channel 16-bit PCM audio output with 20 to 64 kHz sampling rate, typically use 48 kHz
48x Decimation ratio of PDM to PCM audio data
Automatic output sample rates change depends on manually configured input sample rate
110 dB Signal to Noise Ratio
0 ÷ 6 kHz output passband, 10 kHz output stopband
89 dB stopband attenuation in typical condition (2,304 kHz input sample rate and 48 kHz output sample rate)
PCM2PDM converts 16 bit PCM data with low sampling rate to 1 bit PDM data with higher sampling rate, data width is from 16-bit to 24-bit, interpolator factor is 36/48/64/96 using one multiplier.
Single channel 16-bit PCM audio input with 20 to 60 kHz sampling rate, typically use 48 kHz
Single channel 1-bit PDM output with 1 to 3,072 kHz sampling rate, typically use 2,304 kHz
Upsampling factor: 48
Automatic output sample rate's change depends on manually configured input sample rate
Output bandwidth: 0kHz to 20kHz
SNR: 110dB