Vietsemi Technology maintains a broad portfolio of SoC building blocks that provide silicon proven IP for customers who need:
IPs | Description |
|---|---|
| TAP | JTAG Controller |
| UART/USART | Universal Synchronous/Asynchronous Receiver Transmitter |
| SPI | Serial Peripheral Interface |
| QSPI | Quad-Serial Peripheral Interface |
| OSPI | Octal-Serial Peripheral Interface |
| SSI | Synchronous Serial Interface |
| I2C | Inter Integrated Circuit |
| I2S | Inter-IC Sound Bus Controller |
| I3C | Improved Inter-Integrated Circuit |
| GPIO | General Purpose I/O |
Vietsemi Technology provides JTAG Controller (TAP) IP which enables access through the JTAG interface for building designs with efficient, fast, and productive debugging solutions. The IP's size can be scaled by setting parameters.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Master only operation
Slave only operation
Master and slave operation
Clock synchronization
Programmable FIFO watermarks
Interrupt interface
Vietsemi Technology provides Universal Synchronous/Asynchronous Receiver Transmitter (UART/USART) IP which allows the communication of serial character streams between an embedded system and an external device. This communication is done by reading and writing control and data registers. The core implements the RS-232 protocol timing and provides ability to adjust baud rate, parity, stop, and data bits.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Mode programmable: UART, USART
Support programmable baud rates up to 128Kbps
5, 6, 7 or 8 bit characters
Even or Odd or no PARITY bit generation and detection
1, 1.5, 2 STOP bit generation
Support FIFO mode operation
Capability to detect false START bit
Modem mode, programmable auto flow control using CTS and RTS signals
Interrupts generation logic with mask control
Registers accessible through AMBA APB/AXI bus
Capability to detect parity error, over error and frame error
USART mode support synchronous mode using XCK signal, data rate up to 4Mbps
Master only operation
Slave only operation
Master and slave operation
Clock synchronization
Programmable FIFO watermarks
Vietsemi Technology provides Serial Peripheral Interface (SPI) IP which enables an AHB/APB host to access a serial device at high-speed through the SPI interface. The controller supports both Master and Slave modes and consists of a DMA controller to enhance the system performance. The IP can be used in applications such as flash memory card and digital camera.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Programmable operation mode: master or slave
Programmable data length (8, 16, 24, 32 bits)
Programmable Clock polarity and phase (CPOL and CPHA)
Programmable Data Direction (LSB first or MSB first)
Use separated Async. FIFO for Transmitting and Receiving Data, with programmable user-specified runtime-changeable levels
Programmable to use FIFO interrupt
Programmable Clock Divider
Support Multiple Slaves
Support Delay between Slave Select and Serial Clock, Delay between 2 bytes in a transfer
Clock synchronization
Vietsemi Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave. The core operates in various data modes from 4 bits to 32 bits. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.
Supports flash devices from Micron, Macronix, …
Supports QPI PSRAM devices from Apmemory
Supports Single/Dual/Quad SPI protocols
Supports Single Data Rate (SDR) and Double Data Rate (DDR) data transfers
Support APB, AHB and AXI interfaces
Programmable FIFO watermarks
Supports three operating modes: Indirect mode, Memory-mapped mode, Status-flag polling mode
Interrupt and DMA handler
Data prefetching in Memory-mapped mode
Support 8/16/32/64 Bytes Wrapped Burst operation (AHB/AXI interface)
PHY interface with delay locked-loop
Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices. The Controller and PHY IP connects to a system-on-chip (SoC) host through an AMBA® APB bus for the register interface and optional DMA peripheral interface.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
JEDEC xSPI standard compliant
Supports flash devices from Micron, Macronix, Spansion …
Supports PSRAM devices from Apmemory
Supports Single/ Octal SPI protocols
Support APB, AHB and AXI interfaces
Single and double transfer rate
Programmable FIFO watermarks
Supports three operating modes: Indirect mode, status-flag polling mode, memory-mapped mode
Interrupt and DMA handler
Data prefetching in memory-mapped mode
Support AHB, AXI and device wrapping bursts
PHY interface with delay locked-loop
Vietsemi Technology provides Synchronous Serial Interface (SSI) IP which is an interface that is being used with absolute value transmitters, for example position sensors. This interface makes it possible to create a serial data transfer where absolute information concerning a position is transferred. The IP generally is used for point-to-point connections, especially as here a data transfer is required that takes place reliably and securely.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Multi-channel n-bit SSI (n is programmable)
Serial Synchronous Interface
CLOCK and DATA signals are transmitted according to RS422 or RS485 standard
Clock frequencies can be used ranging from 100 kHz to 2 MHz
2 mode Single transmission and Multiple transmissions
Interrupting transmission
Gray/binary decoding for each channel
Automatic communication and Line-break detection
Clock synchronization
I2C controller provides the logic consistent with NXP I2C specification to support the communication of low-speed integrated circuits through I2C bus. The IP facilitates software controllable by application processor through industry-standard AMBA interface. The bus interface is flexible and easily integrated into APB, AHB or AXI system bus.
Master only operation
Slave only operation
Master and slave operation
5 speed modes:
⬥ Standard speed mode (up to 100 Kbps)
⬥ Fast speed mode (up to 400 Kbps)
⬥ Fast speed mode plus (up to 1 Mbps)
⬥ High speed mode (up to 3.4 Mbps)
⬥ Ultra-fast speed mode (up to 5 Mbps)
Singled or combined message protocol
7-bit or 10-bit addressing
Input spike suppression
Clock synchronization
Slave clock stretching
Bus arbitration
General call address
Bus clear operation
Read device ID
Programmable timing parameters, including (tLOW), (tHIGH), (tHD;STA), (tSU;STA), (tHD;DAT), (tSU,STO), (tBUF), and (tSP)
Programmable FIFO watermarks
Interrupt interface
DMA hand-shaking interface
Software interface consistent with AMBA Advanced Peripheral Bus (APB), configurable bus width 8/16/32
Two wire serial interface up to 12.5 MHz using Push-Pull
Legacy I2C Device co-existence on the same Bus (with some limitations)
Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
Legacy I2C messaging
I2C-like Single Data Rate Messaging (SDR)
Optional High Data Rate Messaging Modes (HDR-DDR, HDR-TSL, HDR-TSP)
Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
Reception of In-band Interrupt Support from the I3C Slave devices
Reception of Hot-Join from newly added I3C Slave devices
Synchronous Timing Support and Asynchronous Time Stamping
Master only operation
Slave only operation
Master and slave operation
I2S controller provides an interface between system bus and Inter-IC Sound devices. The controller is compliant with NXP Inter-IC Sound Bus Specification and AMBA APB Specification. Other bus protocols such as AXI-Lite, AHB-Lite, etc are optionally supported.
I2S Bus Specification
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
Master operation
Slave operation
Master and slave operation
Stereo audio
I2S, left-justified, right-justified mode
Audio bit-depth 8/12/16/24/32
Up to 192 Khz sample rate
System bus width 8/16/32
Programmable FIFO watermarksspan>
Interrupt interface
DMA interface
Software interface consistent with AMBA Advanced Peripheral Bus (APB)
I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated circuits through I3C bus.
The IP facilitates software controllable by application processor through industry-standard AMBA interface. The bus interface is flexible and easily integrated into APB, AHB or AXI system bus.
MIPI I3C specification v1.1
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Two wire serial interface up to 12.5 MHz using Push-Pull
Legacy I2C Device co-existence on the same Bus (with some limitations)
Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
Legacy I2C messaging
I2C-like Single Data Rate Messaging (SDR)
Optional High Data Rate Messaging Modes (HDR-DDR, HDR-TSL, HDR-TSP)
Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
Reception of In-band Interrupt Support from the I3C Slave devices
Reception of Hot-Join from newly added I3C Slave devices
Synchronous Timing Support and Asynchronous Time Stamping
Master only operation
Slave only operation
Master and slave operation
Transmission modes: Single Data Rate (SDR) Mode
Dynamic Address Assignment
Host-join request
Secondary master request to be current master
Slave interrupt request
Support for I3C common command codes
Error Detection and Recovery Methods for SDR
Transmission modes: Single Data Rate (SDR) Mode
Dynamic Address Assignment
Host-join
In-Band Interrupt
Error Detection and Recovery Methods for SDR
Detect HDR Exit Pattern
Support for I3C common command codes:
⬥ Broadcast CCCs
⚬ RSTDAA
⚬ ENTDAA
⚬ ENEC, DISEC
⚬ ENTAS0, ENTAS1, ENTAS2, ENTAS3
⚬ SETMWL, SETMRL
⬥ Direct CCCs
⚬ SETDASA
⚬ SETNEWDA
⚬ GETSTATUS
⚬ ENEC, DISEC
⚬ ENTAS0, ENTAS1, ENTAS2, ENTAS3
⚬ SETMWL, SETMRL
⚬ GETMWL, GETMRL
⚬ GETMXDS
⚬ GETPID, GETBCR, GETDCR
⚬ GETXTIME
Vietsemi Technology provides General Purpose I/O IP which cosists of up to 32 I/O ports that can be programmed individually for input, output, or bidirectional operation. Each port can be programmed to trigger the GPIO interrupt on level (high, low) or edge (rising, falling, any) events. The IP serves as additional means of communication between various components of the system on chip (SoC).
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Programmable number of GPIO signals which is input, output or bidirectional operation
Programmable interrupt with some event types
Bypass mode to control directly each GPIO port
Support internal register to capture input or output data
Support open drain and pull up/down option
Clock synchronization
Programmable FIFO watermarks
Interrupt interface
Software interface consistent with AMBA APB Bus, configurable bus width 8/16/32