Vietsemi Technology maintains a broad portfolio of SoC building blocks that provide silicon proven IP for customers who need:
IPs | Description |
|---|---|
| RTC | Real-time Clock |
| TTC | Triple Timer Counter |
| WDT | Watchdog Timer |
| DMA | Direct Memory Access |
| Interrupt Controller | Interrupt Controller |
| PCIe Controller | PCIe 3/4/5 Controller |
| AMBA Bus Interface | AMBA Bus (APB, AHB, AXI, AXI-Lite, AXI Stream) |
| PWM | Pulse Width Modulator |
| CXL Controller | CXL 3.0 Controller |
| UCIe Controller | UCIe 1.1 Controller |
Vietsemi Technology provides Real Time Clock (RTC) IP which is used to avoid confusion with ordinary hardware clocks which are only signals that govern digital electronics, and do not count time in human units. The IP is a low-power, cost-effective solution for demanding applications and offers SoC integrators the advanced capabilities and support the requirements of high-performance designs and implementations.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Master only operation
Slave only operation
Master and slave operation
Clock synchronization
Programmable FIFO watermarks
Interrupt interface
Vietsemi Technology provides Triple Timer Counter (TTC) IP with three independent timer/counter modules that can each be clocked using either the system clock or an externally derived clock. In addition, each counter can independently pre-scale its selected clock with various counting modes.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Uses the AMBA APB protocol
Three independently programmable 32-bit timer/counters
Internal (pclk) or external (clk) clock source (one for each timer/counter)
Three interrupts, one from each timer/counter
Interrupt generated either on overflow or at regular intervals and when count matches a programmable value
32bit prescaler, for clock speed selection
Three output waveforms, one from each counter (generated using overflow or interval and Match 1 interrupts)
An event timer measures length of each external clock pulse (high or low duration)
Counters can be programable incrementing or decrementing and current value of each counters can be read at any time
Vietsemi Technology provides Watchdog Timer (WDT) IP which is used to prevent system lockup if software becomes trapped in a deadlock by generating a system reset, an interrupt, or an external signal. The IP is programmable by a standard APB Slave peripheral which is used periodically by Software to control the watchdog by writing to it to reset its timeout counters.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
32 bit APB bus width.
WDT can perform two types of operations when timeout occurs:
Generate a system reset.
First generate an interrupt and even if it is cleared (or not cleared) by the service routine by the time a second timeout occurs then generate a system reset.
Pause mode for debugging
Programmable reset pulse length
Prevention of accidental restart of the watchdog counter
Prevention of accidental disabling of the watchdog counter
32 bits WDT counter width
Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
Optional external clock signal to control the rate at which the counter counts
Optional support for asynchronous external timer clock. With this feature enabled, the timer interrupt and system reset can be generated, even when the APB bus clock is switched off
Software interface consistent with AMBA Advanced Peripheral Bus (APB), Advanced High-performance bus (AHB) or Advanced eXtensible Interface (AXI)
The DMA control the DMA transfers data between different points in the memory space without intervention of the CPU. The DMA is generally used to replace two CPU functions: memory copy and transfer data between memory and peripheral (peripheral devices such as SPI, UART, GPIO, I2C, I2S, WDT, etc.)
Support 1 to 16 channels (Parameter Configuration)
Support maximum 8 peripherals can connect to 1 DMA channel (Parameter Configuration)
Channel Arbitration
Multiple transfer direction: memory to memory, memory to peripheral, peripheral to memory
Single APB Programming Interface (Programming Registers)
2 AXI4 Master Ports (Parameter Configuration)
Asynchronus AXI4/APB Interfaces
AXI4 Data Width: 32, 64, 128, 256 or 512 bits (Parameter Configuration)
AXI4 Address Width: Up to 32 bits (Parameter
Configuration)
Support source address, destination address,
data tran unaligned with AXI4 data size
Single FIFO data per channel
Automatic packing/unpacking of data to fit FIFO width
Support timeout monitoring
Data swapping endian mode
Interrupt for DMA transfer and channel status
Support Scatter-Gather mode
Support Circular mode
Support Double Buffer mode
Support 1D-2D transfer mode
Interrupt Controller (ICTRL) is an APB slave peripheral that can be used to control interrupts of devices when that send interrupts to CPU.
2 to 32 IRQ normal interrupt sources
1 to 8 FIQ fast interrupt sources (optional)
Software interrupt
Vectored interrupt (optional)
Priority filtering
Masking
Programmable interrupt priorities (after configuration)
Vector port interface that allows a processor to sample the vector address associated with the current highest priority irq without a bus access
Vietsemi PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications.
The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1).
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Master only operation
Slave only operation
Master and slave operation
Clock synchronization
Programmable FIFO watermarks
Interrupt interface
Vietsemi Technology provides Pulse Width Modulator (PWM) IP which can easily modify the shape of the waveform during operation, adjusting both the period and high time through an AMBA® APB slave interface. The PWM IP also incorporates all basic functions needed for standalone operation.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Master only operation
Slave only operation
Master and slave operation
Clock synchronization
Programmable FIFO watermarks
Interrupt interface
Vietsemi Technology ...
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Vietsemi Technology ...
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0