Vietsemi Technology maintains a broad portfolio of SoC building blocks that provide silicon proven IP for customers who need:
IPs | Description |
|---|---|
| SDRAM PHY & Controller | Dynamo DDR2/DDR3/DDR4/DDR5/LPDDR2/LPDDR3/LPDDR4/LPDDR5 multichannel external memory controller |
| eMMC PHY & Controller | EMMC controller 4.0/5.0 |
| NVLPDDR4 Controller | Dynamo NVLPDDR4 memory controller |
| SDR Controller | Dynamo SDR memory controller |
| HBM Controller | HBM 2e memory controller |
| SD Host Controller | SD host controller. It supports both legacy and ultra-high speed II (UHS-II) interfaces. |
| UHS PSRAM Controller | UHS PSRAM controller |
| ONFI Controller | ONFI Controller 4.2/5.0 |
| Memory Test & Repair | A memory BIST solution which has been optimized for Vietsemi memories |
Vietsemi Technology's hardened DDR5/4/3/2 SDRAM PHY and LPDDR5/4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 4266 Mbps. It is fully compliant with the DFI 4.0/5.0/5.1 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST). In addition, our PHY IP is optimized to provide a complete solution when combined with Vietsemi Technology's DDRx and LPDDRx SDRAM Memory Controller IP.
Vietsemi Technology offers high performance DDR5/4/3/2 SDRAM and LPDDR5/4/3/2 SDRAM Memory Controller IP across a broad range of process technologies. These Memory Controllers are fully compliant with the DFI 4.0/5.0/5.1 specification, support speeds up to 4266 Mbps, and are optimized to provide a comprehensive solution when combined with Vietsemi Technology's DDR PHY IP.
Supports JEDEC Standard DDR4/3/2 and LPDDR4/3/2 SDRAM
DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
Supports speeds of up to 4266 Mbps (2133 MHz) LPDDR4
Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
Built-in Gate Training, Read/Write Leveling, and VREF Training
Multi-Port Configurable AXI4 Interface with QoS Signaling
Single AXI4-Lite Programming Interface
Multi-port arbitration engine with programmable dynamic priority algorithm ensure high performance and low-latency.
Pipeline Option for Frequency versus Latency Tradeoff
Fully configurable for various performances and requirements, ensuring maximum performance for different system environments.
FPGA portable. Compatible with Xilinx PHY and Altera PHY.
Available with BFM verification suite.
Support for AXI4 Dynamic QoS Signaling for Non-Blocking Communications
Support for Low-Latency Bypass Ports/Channels
Advanced Dynamic QoS Support Based on the Queuing Theory and Traffic Hysteresis
Forward Priority Propagation for Queued Transactions
Traffic-Configurable Address Mapping Scheme with Two Column Segments
Run-time Configurable Timing Parameters and Memory Settings
Intelligent Bank Management and Auto-Precharge Scheduling
Intelligent Traffic Direction Aggregation and Switching
Programmable and Dynamic Auto-refresh Scheduling
Proprietary Non-Blocking Priority-Based DDRx/LPDDRx SDRAM Control and Data Buses Access Algorithm
Real-Time QoS Capability
Multi-Channel Configuration (Up to 4)
Multi-Rank Configuration (Up to 4)
Support for Out-of-Order Memory Access
DDR3 Controller on Xilinx Board
LPDDR3 Controller on Xilinx Board
DDR3L Controller on Xilinx Board
DDR4 Controller on Xilinx Board
Vietsemi Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded Multi-Media-Card (eMMC) version 5.1 into any system on chip (SoC).
JEDEC eMMC Specification Version 5.1.
AMBA, Advanced Extensible Interface (AXI) Specification Version 4.0.
AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0.
32-bit and 64-bit system data bus.
32-bit and 64-bit system addressing.
64 and 128 bit DMA Descriptor length.
Interrupts functionality.
Supports both Asynchronous and Synchronous AXI4 Interface: The Master and the Host Controller operate at the same clock rate or different clock rates.
Programmed Input/Output (PIO) mode on the Host Bus Slave interface.
Direct Memory Access (SDMA and ADMA2) mode on the Host Bus Master interface.
Configurable FIFO size to support different block sizes 512B and 4KB.
HS400 high speed interface timing mode of up to 400 MB/s data rate.
Transfers the data in HS400, HS200, DDR52, SDR52 modes.
4KB block support.
Tuning for HS200 mode.
Command Queuing for High Performance data transfers with Hardware Acceleration.
Enhanced strobe function for reliable operation at HS400 mode.
Host clock rate variable between 0 and 200 MHz.
Supports 1-bit, 4-bit and 8-bit data interface.
Supports legacy modes (Default Speed, High Speed).
CRC7 for command and CRC16 for data integrity.
Supports multiple boot mode.
Vietsemi Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded Multi-Media-Card (eMMC) version 5.1 into any system on chip (SoC).
JEDEC eMMC Specification Version 5.1.
Vietsemi Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded Multi-Media-Card (eMMC) version 5.1 into any system on chip (SoC).
JEDEC eMMC Specification Version 5.1.
Vietsemi Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded Multi-Media-Card (eMMC) version 5.1 into any system on chip (SoC).
JEDEC eMMC Specification Version 5.1.
UHS PSRAM external memory controller is interfaced to control PSRAM devices. The controller is fully programmable and configurable, flexible to customers' needs.
Single Channel Configuration (1 channel for PSRAM)
Single APB Programming Interface (Programming Registers)
Single AXI4 Interfaces Configuration (1 AXI4 Interfaces)
Programmable Timing Registers
Programmable PSRAM Operation Mode (Through MRW)
Dynamic Address Mapping Scheme
Automatic Periodic Refresh
1:1/1:2/1:4 Frequency Ratio System
Asynchronous/Synchronous AXI4/APB Interfaces
Page Read Access (PRA) input through DM pin
Wrap burst in 16/32/64/128 Bytes length
Data write mask for write operation through DM pin
PHY features support:
⬥ DFI 3.1 Compliance
⬥ 1:2 frequency ratio support
⬥ DDR3/2 LPDDR3/2 PHY- Independent training mode for gate, write leveling
⬥ 8-bit DQ
Vietsemi Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded Multi-Media-Card (eMMC) version 5.1 into any system on chip (SoC).
JEDEC eMMC Specification Version 5.1.
Vietsemi Technology now provides a memory BIST solution which has been optimized for Dolphin memories. It supports all Dolphin memory compilers, including SRAM and RF.
Fully automated MBIST RTL and Gate flow
Fully supported BIST test, diagnosis and soft/hard repair
Fully supported eFuse controller for automated hard repair
Analyze RTL design or netlist to identify memories
Plan MBIST engines
Verify stand-alone
Insert into RTL design or netlist
Verify partition level
Top level hookup to JTAG
Fully supported P1500 interface and Tap controller
Verify top level
Generate test patterns and SVF file
Incremental repair capability
Programmable March-style algorithm
APB interface for BIST test and fuse operation
Diagnosis test, Characterization test and SVF debug flow
Fully supported ICL/PDL of IEEE 1687
Automated subchip integration flow